1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating such a semiconductor device. More particularly, the present invention relates to a semiconductor device including a retail silicide layer, and a method of fabricating this semiconductor device.
2. Description of the Background Art
For the purpose of realizing increase in the integration density and speed of a semiconductor device, further reduction in the design rule has been considered these few years. At the present stage, a prototype of a 256M DRAM (Dynamic Random Access Memory) and a prototype of a CMOS (Complementary Metal Oxide Semiconductor) transistor having a gate length of 1 .mu.m are disclosed. By such progress in the miniaturization of a transistor, reduction in the design size according to the scaling rule, and increase in the speed of operation thereof are now expected.
Although the channel resistance can be reduced by simply reducing the size of a transistor, the parasitic resistance in the impurity diffusion layer that becomes the source and drain region and resistance at the contact between conductors (contact resistance; will become equal to or greater than the channel resistance. This is a bottleneck in increasing the operation speed. Furthermore, the resistance of the gate interconnection (electrode) must be reduced in order to increase the operation speed while implementing miniaturization.
The silicide (self-aligned silicide) method is proposed (T. Yoshida et. al.: J. Electrochemi. Soc., Vol. 137. No. 6, 1990, pp. 1914-1917) as a method of reducing the parasitic resistance of the source and drain regions and the interconnection resistance of the gate electrode at the same time.
A method of fabricating a conventional p channel MOS transistor having a silicide structure and a LDD (Lightly Doped Drain) structure will be described hereinafter with reference to FIGS. 1A-1F.
Referring to FIG. 1A, an element isolation insulation film 2 is formed on a main surface of an n type monocrystalline silicon substrate 1 employing the LOCOS (Localized Oxidation of Silicon) method. Then, a silicon oxide film is formed on the main surface of substrate 1 by thermal oxidation. Next, a doped polysilicon film having boron doped on the silicon oxide film is formed by CVD (Chemical Vapor Deposition). The doped polysilicon film and the silicon oxide film are patterned to a desired configuration to form a gate insulation film 3 and a gate electrode 4.
Referring to FIG. 1B, boron ions (B+) are implanted into the main surface of substrate 1 using gate electrode 4 as a mask. An impurity region 5 of low concentration is formed in self alignment.
Referring to FIG. 1C, a silicon oxide film is formed all over the surface of substrate 1 shown in FIG. 1B by CVD. Then, this silicon oxide film is etched back all over to form a sidewall spacer 6 at the sidewall of gate electrode 4. Using gate electrode 4 and sidewall spacer 6 as a mask, boron fluoride ions (BF.sub.2.sup.+) are implanted into a main surface of substrate 1 to form an impurity region 7 of high concentration in self alignment.
By the above processes, a p channel MOS transistor 8 of an LDD structure is completed including the source and the drain regions formed of impurity region 5 of low concentration and impurity region 7 of high concentration, respectively.
Referring to FIG. 1D, a native oxide film formed on the main surface of substrate 1 is removed by isotropic etching. Then, a titanium film 9 (for example, 30 nm in film thickness) is formed by magnetron sputtering.
Referring to FIG. 1E, the device having the structure shown in FIG. 1D is subjected to the first heat treatment at the processing temperature of 600-700.degree. C. by a thermal treating process in an electric furnace or RTA (Rapid Thermal Annealing). As a result, as titanium silicide (TiSi.sub.2) film 10 is formed in self alignment at the region where titanium film 9 and silicon substrate 1 are in contact and the region where titanium film 9 and polysilicon gate electrode 4 are in contact. Titanium silicide film 10 formed by the first heat treatment has a C49 phase of a relatively high resistance.
The processing time is approximately 30 minutes when the thermal treating process in an electric furnace is employed and approximately 30 seconds when the RTA method is employed. Titanium silicide film 10 is not formed where titanium film 9 and element isolation insulation film 2 are in contact or where titanium film 9 and sidewall spacer 6 are in contact by this heat treatment.
Then, titanium film 9 that is not silicided is removed by wet etching using a mixed solution of hydrogen peroxide, ammonia, and water heated to approximately 60.degree. C. (mixture ratio is H.sub.2 O.sub.2 :NH.sub.4 OH:H.sub.2 O=1:1:5) to leave only titanium silicide film 10.
Then, the second heat treatment is carried out at the processing temperature of 750-900.degree. C. by a thermal treating process in an electric furnace or RTA. The processing time of the second heat treatment is identical to that of the first heat treatment. By the second heat treatment, the titanium silicide of the C49 phase is converted into a C54 phase of a relatively low resistance.
Referring to FIG. 1F, following deposition of an interlayer insulation film 11 all over the device shown in FIG. 1E, a contact hole 12 is formed in interlayer insulation film 11 by anisotropic etching to expose a portion of titanium silicide film 10. Then, contact hole 12 is filled with a metal material by sputtering to form a metal interconnection layer 13.
According to the MOS transistor 8 shown in FIG. 1F, titanium silicide film 10 is formed on the surface of source/drain region 14 and gate electrode 4. Therefore, the parasitic resistance of the source/drain region and the interconnection resistance of the gate electrode can be reduced at the same time.
FIGS. 1A-1F show fabrication of a p channel MOS transistor. When an n channel MOS transistor of an LDD structure is to be formed, an n type impurity (for example, phosphorus, arsenic or the like) are ion-implanted into the main surface of a p type substrate.
FIG. 1F shows one element formation region surrounded by element isolation insulation film 2. Three contact holes 12 are formed in the depicted region. A plurality of element formation regions isolated by element isolation insulation film 2 are present on the main surface of substrate 1. An MOS transistor located at one element formation region is electrically connected to an MOS transistor located at another element formation region via metal interconnection layer 13. Metal interconnection layer 13 extends on interlayer insulation film 11 to be connected to each MOS transistor via the contact hole. According to this interconnection structure, the number of contact holes 12 is increased. Also, the length of metal interconnection layer 13 becomes relatively greater.
A longer metal interconnection layer 13 results in a higher interconnection resistance, so that the load on the transistor is increased. As a result, the operation speed of the device will be degraded.
When a contact hole is to be formed, some margin must be provided in the area of the device taking into consideration offset in the mask alignment. This means that increase in the device area cannot be avoided if the number of contact holes to be formed is increased.
These problems are apparent by referring to FIGS. 2-5.
Referring to FIG. 2 showing a plane layout, a plurality of element formation regions 16 are separated by an element isolation insulation film 15. A gate interconnection layer 17 extends so as to traverse the plurality of element formation regions 16, and is connected to the upper metal interconnection layer 18 via a contact hole portion 20. The impurity diffusion layer in element formation region 16 that becomes the source/drain region is connected to the upper metal interconnection layer 18 via respective contact holes 19. A metal silicide layer is formed above the impurity diffusion layer that is the subsequent source/drain region and above gate interconnection layer 17.
Metal interconnection layer 18 shown in FIG. 3 electrically connects the impurity diffusion layer in element formation region 16 with gate interconnection layer 17 extending over element isolation insulation film 15 via two contact holes 19 and 20.
Metal interconnection layer 18 shown in FIG. 4 electrically connects the impurity diffusion layers in adjacent element formation regions 16 via two contact holes 19.
FIG. 5 shows an impurity diffusion layer 21 having an ideal size, and a contact hole 22 for forming contact with impurity diffusion layer 21. Impurity diffusion layer 21 becomes the source/drain region of a transistor. Considering the mask alignment accuracy by lithography of the current stage, slight offset in the position of contact hole 22 cannot be avoided. The position of an offset contact hole is designated by 22a. The impurity diffusion layer that is to be formed must be provided taking account of this contact hole position offset. It is therefore necessary to form an impurity diffusion layer 21a larger than a desired size. As mentioned before, increase in the device area cannot be avoided if the number of contact holes to be formed is increased.